A Non-sequential Phase Detector for PLL-based High-Speed Data/Clock Recovery
نویسندگان
چکیده
* This work was supported, in part, by Texas Instruments Inc., RocketChips Inc. and the R. J. Carver trust. Abstract – The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at highspeed. This paper presents a new Phase Detector (PD) that can be used for high-speed random data/clock recovery. In contrast to most existing structures which are speed-limited by sequential logic circuits. It exploits the leading and lagging signals from the VCO which greatly simplifies the PD structure. Using the HSPICE simulator and HP 0.35u standard CMOS process models, simulation results show that the PD can operate at 2GHz over the 0°C to 100°C temperature range and over fast and slow process corners.
منابع مشابه
A 2
A Phase Locked Loop (PLL) design based on a new phase detector (PD) is presented. It can be used as a part of data/clock recovery (DCR) systems targeting the applications of 2Gbit/s-3Gbit/s range ethernet and optic fiber transceivers in current semiconductor processes. A key component in the circuit is a new non-sequential PD that provides for very high speed operation. Using TSMC 0.25u CMOS pr...
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